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1 ? fn6044.4 isl43410 low-voltage, single supply, dpdt high performance analog switch the intersil isl43410 is a precision, bidirectional, analog switch configured as a double pole/double throw (dpdt) switch. the isl43410 is designed to operate from a single +2v to +12v supply. it is equipped with an inhibit pin to simultaneously open all signal paths. on-resistance is 115 with a +5v supply, 45 with a +12v supply, and 190 with a +3v supply. each switch can handle rail-to-rail analog signals. the of f-leakage current is only 3na at +25c or 5na at +85c. all digital inputs have 0.8v to 2.4v logic thresholds ensuring ttl/cmos logic compatibility when using a single +5v supply. some of the smallest packages are available, alleviating board space limitations, and making intersil?s newest line of low-voltage switches an ideal solution. the isl43410 is a dpdt, which is perfect for use in 2-to-1 multiplexer applications. table 1 summarizes the performance of this switch. related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ? application note an557 ?recommended test procedures for analog switches? ? application note an520 ?cmos analog multiplexers and switches; specifications and application considerations? ? application note an1034 ?analog switch and multiplexer applications? features ? fully specified at 3v, 5v, and 12v supplies for 10% tolerances ? on-resistance (r on ), v s = 5v . . . . . . . . . . . . . . . . . 100 ?r on matching between channels . . . . . . . . . . . . . . . . . . <2 ? low charge injection . . . . . . . . . . . . . . . . . . . . . . 3pc (max) ? single supply operation. . . . . . . . . . . . . . . . . . . +2v to +12v ? low power consumption (p d ) . . . . . . . . . . . . . . . . . . . .<3w ? low off leakage current . . . . . . . . . . . . . . . . . . . . . . 5na ? fast switching action (v s = 5v) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns ? guaranteed break-before-make ? ttl, cmos compatible ? available in 10 ld msop and 16 ld qfn packages ? pb-free available (rohs compliant) applications ? battery-powered, handheld, and portable equipment ? communications systems -radios - telecom infrastructure - adsl, vdsl modems ? test equipment - medical ultrasound - electrocardiograph - magnetic resonance imaging - ct and pet scanners (mri) -ate ? audio and video switching ? various circuits - +3v/+5v dacs and adcs - sample and hold circuits - operational amplifier gain switching networks - high frequency analog switching - high speed multiplexing - integrator reset circuits table 1. features at a glance configuration dpdt 12v r on 45 12v t on /t off 25ns/24ns 4.5v r on 115 4.5v t on /t off 60ns/30ns 3v r on 190 3v t on /t off 120ns/45ns packages 10 ld msop, 16 ld 3x3 qfn data sheet may 12, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2003, 2004, 2006, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6044.4 may 12, 2008 pinouts (note 1) isl43410 (10 ld msop) top view isl43410 (16 ld 3x3 qfn) top view no1 com1 nc1 inh gnd v+ com2 no2 nc2 add 1 2 3 4 5 10 9 8 7 6 logic note: 1. switches shown for logic ?0? inputs. 1 3 4 15 nc nc nc no1 v+ com2 no2 nc2 16 14 13 2 12 10 9 11 6 578 add nc nc nc com1 nc1 inh gnd truth table isl43410 inh add switch on 1 x none 00ncx 01nox note: logic ?0? 0.8v. logic ?1? 2.4v, with v s between 3.3v and 11v. pin descriptions pin function v+ system power supply input (+2v to +12v) gnd ground connection inh digital control input. connect to gnd for normal operation. connect to v+ to turn all switches off. comx analog switch common pin nox analog switch normally open pin ncx analog switch normally closed pin add address input pin nc no internal connection ordering information part number part marking temp. range (c) package pkg. dwg. # isl43410iu 3410 -40 to +85 10 ld msop m10.118 ISL43410IU-T* 3410 -40 to +85 10 ld msop m10.118 isl43410iuz (note) 3410z -40 to +85 10 ld msop (pb-free) m10.118 isl43410iuz-t* (note) 3410z -40 to +85 10 ld msop (pb-free) m10.118 isl43410ir 410i -40 to +85 16 ld qfn l16.3x3 isl43410ir-t* 410i -40 to +85 16 ld qfn l16.3x3 isl43410irz (note) 341z -40 to +85 16 ld qfn (pb-free) l16.3x3 isl43410irz-t* (note) 341z -40 to +85 16 ld qfn (pb-free) l16.3x3 *please refer to tb347 for details on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. isl43410
3 fn6044.4 may 12, 2008 absolute maximum rati ngs thermal information v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 15v input voltages inh, no, nc, add (note 2) . . . . . . . . . . . . -0.3v to ((v+) + 0.3v) output voltages com (note 2) . . . . . . . . . . . . . . . . . . . . . . . -0.3v to ((v+) + 0.3v) continuous current (any terminal) . . . . . . . . . . . . . . . . . . . . . 30ma peak current no, nc, or com (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . . . 40ma operating conditions temperature range isl43410ix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to 85c thermal resistance (typical) ja (c/w) jc (c/w) 10 ld msop package (note 3) . . . . . . 190 n/a 16 ld qfn package (notes 4, 5). . . . . 58 11 maximum junction temperature (plastic package). . . . . . . +150c moisture sensitivity (see technical brief tb363) all packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . level 1 maximum storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 2. signals on nc, no, com, add, or inh exce eding v+ or gnd are clamped by internal di odes. limit forward diode current to maximu m current ratings. 3. ja is measured with the component mounted on a low effective therma l conductivity test board in free air. see tech brief tb379 fo r details. 4. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications +5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 6), unless otherwise specified. parameter test conditions temp (c) min (notes 7, 12) typ max (notes 7, 12) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 4.5v, i com = 1.0ma, v no or v nc = 3.5v, (see figure 5, note 11) 25 - 115 125 full - - 150 r on matching between channels, r on v+ = 4.5v, i com = 1.0ma, v no or v nc = 3.5v, (notes 9, 11) 25 - 1 3 full - - 5 r on flatness, r flat(on) v+ = 5.5v, i com = 1.0ma, v no or v nc = 1.5v, 2.5v, 3.5v, (notes 10, 11) 25 - 12 13 full - 13 18 no or nc off leakage current, i no(off) or i nc(off) v+ = 5.5v, v com = 1v, 4.5v, v no or v nc = 4.5v, 1v (note 8) 25 -3 - 3 na full -5 - 5 na com off leakage current, i com(off) v+ = 5.5v, v com = 4.5v, 1v, v no or v nc = 1v, 4.5v (note 8) 25 -3 - 3 na full -5 - 5 na com on leakage current, i com(on) v + = 5.5v, v com = 1v, 4.5v, or v no or v nc = 1v, 4.5v, or floating (note 8) 25 -3 - 3 na full -5 - 5 na digital input characteristics input voltage high, v inh full 2.4 1.4 - v input voltage low, v inl full - 1.3 0.8 v input current, i inh , i inl v+ = 5.5v, v in = 0v or v+ full -0.5 - 0.5 a dynamic characteristics inhibit turn-on time, t on v+ = 4.5v, v no or v nc = 3v, r l = 300 , c l = 35pf, v in = 0 to 3 (see figure 1) 25 - 60 - ns full - 75 - ns isl43410
4 fn6044.4 may 12, 2008 inhibit turn-off time, t off v+ = 4.5v, v no or v nc = 3v, r l = 300 , c l = 35pf, v in = 0 to 3 (see figure 1) 25 - 30 - ns full - 35 - ns address transition time, t trans v+ = 4.5v, v no or v nc = 3v, r l = 300 , c l = 35pf, v in = 0 to 3 (see figure 1) 25 - 61 - ns full - 76 - ns break-before-make time delay, t d v+ = 5.5v, r l = 300 , c l = 35pf, v no = v nc = 3v, v in = 0 to 3 (see figure 3) full - 16 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 (see figure 2) 25 - 0.3 - pc off-isolation r l = 50 , c l = 5pf, f = 1mhz (see figure 4) 25 - 75 - db crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 1mhz (see figure 6) 25 - -85 - db no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 - 4 - pf com off capacitance, c com(off) f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 - 6 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 - 12 - pf power supply characteristics power supply range full 2 - 12 v positive supply current, i+ v+ = 5.5v, v in = 0v or v+, all channels on or off full -1 0.0001 1 a electrical specifications +5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 6), unless otherwise specified. (continued) parameter test conditions temp (c) min (notes 7, 12) typ max (notes 7, 12) units electrical specifications +3v supply test conditions: v+ = +2.7v to +3.6v, gnd = 0v, v ah = 2.4v, v al = 0.8v (note 6), unless otherwise specified. parameter test conditions temp (c) min (notes 7, 12) typ max (notes 7, 12) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 3.0v, i com = 1.0ma, v no or v nc = 1.5v (see figure 5, note 11) 25 - 190 220 full - - 250 r on matching between channels, r on v+ = 3.0v, i com = 1.0ma, v no or v nc = 1.5v (notes 9, 11) 25 - 1 3 full - - 5 r on flatness, r flat(on) v+ = 3.0v, i com = 1.0ma, v no or v nc = 0.5v, 1.5v (notes 10, 11) 25 - 48 90 full - - 90 no or nc off leakage current, i no(off) or i nc(off) v+ = 3.6v, v com = 1v, 3v, v no or v nc = 3v, 1v (note 8) 25 -3 - 3 na full -5 - 5 na com off leakage current, i com(off) v+ = 3.6v, v com = 3v, 1v, v no or v nc = 1v, 3v (note 8) 25 -3 - 3 na full -5 - 5 na com on leakage current, i com(on) v + = 3.6v, v com = 1v, 3v, or v no or v nc = 1v, 3v, or floating (note 8) 25 -3 - 3 na full -5 - 5 na digital input characteristics input voltage high, v inh full 2.0 1.0 - v input voltage low, v inl full - 0.8 0.5 v input current, i inh , i inl v+ = 3.6v, v in = 0v or v+ full -0.5 - 0.5 a isl43410
5 fn6044.4 may 12, 2008 dynamic characteristics inhibit turn-on time, t on v+ = 2.7v, v no or v nc = 1.5v, r l = 300 , c l = 35pf v in = 0 to 3 (see figure 1) 25 - 144 - ns full - 165 - ns inhibit turn-off time, t off v+ = 2.7v, v no or v nc = 1.5v, r l = 300 , c l = 35pf v in = 0 to 3 (see figure 1) 25 - 53 - ns full - 60 - ns address transition time, t trans v+ = 2.7v, v no or v nc = 1.5v, r l = 300 , c l = 35pf v in = 0 to 3 (see figure 1) 25 - 145 - ns full - 180 - ns break-before-make time delay, t d v+ = 3.6v, r l = 300 , c l = 35pf, v no or v nc = 1.5v v in = 0 to 3 (see figure 3) full - 35 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 (see figure 2) 25 - 0.5 - pc off-isolation r l = 50 , c l = 5pf, f = 1mhz (see figure 4) 25 - 75 - db crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 1mhz (see figure 6) 25 - -85 - db no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 - 4 - pf com off capacitance, c com(off) f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 - 6 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 - 12 - pf power supply characteristics positive supply current, i+ v+ = 3.6v, v in = 0v or v+, all channels on or off full -1 0.0001 1 a electrical specifications +3v supply test conditions: v+ = +2.7v to +3.6v, gnd = 0v, v ah = 2.4v, v al = 0.8v (note 6), unless otherwise specified. (continued) parameter test conditions temp (c) min (notes 7, 12) typ max (notes 7, 12) units electrical specifications + 12v supply test conditions: v+ = +10.8v to +13.2v, gnd = 0v, v inh = 4v, v inl = 0.8v (note 6), unless otherwise specified. parameter test conditions temp (c) min (notes 7, 12) typ max (notes 7, 12) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 12.0v, i com = 1.0ma, v no or v nc = 9v (see figure 5, note 11) 25 - 45 50 full - - 70 r on matching between channels, r on v+ = 12.0v, i com = 1.0ma, v no or v nc = 9v (notes 9,11) 25 - 0.5 3 full - - 5 r on flatness, r flat(on) v+ = 13.2v, i com = 1.0ma, v no or v nc = 3v, 6v, 9v (notes 10, 11) 25 - 5 6 full - - 10 no or nc off leakage current, i no(off) or i nc(off) v+ = 13.0v, v com = 1v, 12v, v no or v nc = 12v, 1v (note 7) 25 -3 - 3 na full -5 - 5 na com off leakage current, i com(off) v+ = 13.0v, v com = 12v, 1v, v no or v nc = 1v, 12v (note 7) 25 -3 - 3 na full -5 - 5 na com on leakage current, i com(on) v + = 13.0v, v com = 1v, 12v, v no or v nc = 1v, 12v or floating (note 7) 25 -3 - 3 na full -5 - 5 na digital input characteristics input voltage high, v inh full 2.9 2.5 - v input voltage low, v inl full - 2.3 0.8 v input current, i inh , i inl v+ = 13v, v in = 0v or v+ full -0.5 - 0.5 a isl43410
6 fn6044.4 may 12, 2008 dynamic characteristics inhibit turn-on time, t on v + = 10.8v, v no or v nc = 10v, r l = 300 , c l = 35pf v in = 0 to 4, (see figure 1) 25 - 25 - ns full - 30 - ns inhibit turn-off time, t off v + = 10.8v, v no or v nc = 10v, r l = 300 , c l = 35pf v in = 0 to 4, (see figure 1) 25 - 24 - ns full - 30 - ns address transition time, t trans v + = 10.8v, v no or v nc = 10v, r l = 300 , c l = 35pf v in = 0 to 4, (see figure 1) 25 - 35 - ns full - 50 - ns break-before-make time delay, t d v + = 13.0v, r l = 300 , c l = 35pf, v no or v nc = 10v v in = 0 to 4 (see figure 3) full - 9 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 (see figure 2) 25 - 1.2 - pc off-isolation r l = 50 , c l = 5pf, f = 1mhz, (see figure 4) 25 - 75 - db crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 1mhz, (see figure 6) 25 - -85 - db no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v, (see figure 7) 25 - 4 - pf com off capacitance, c com(off) f = 1mhz, v no or v nc = v com = 0v, (see figure 7) 25 - 6 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v, (see figure 7) 25 - 12 - pf power supply characteristics positive supply current, i+ v+ = 13.0v, v in = 0v or v+, all channels on or off full -1 0.0001 1 a notes: 6. v in = input voltage to perform proper function. 7. the algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 8. leakage parameter is 100% tested at high te mp, and guaranteed by correlation at +25c. 9. r on = r on (max) - r on (min). 10. flatness is defined as the difference between the maximum and minimum value of on-resistance over the specified analog signa l range. 11. limits established by characteri zation and are not production tested. 12. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established b y characterization and are not production tested. test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for other switches. c l includes fixture and stray capacitance. figure 1b. test circuit electrical specifications + 12v supply test conditions: v+ = +10.8v to +13.2v, gnd = 0v, v inh = 4v, v inl = 0.8v (note 6), unless otherwise specified. (continued) parameter test conditions temp (c) min (notes 7, 12) typ max (notes 7, 12) units 50% t r < 20ns t f < 20ns t on 3v 0v t off logic input switch output 90% 0v 90% v out v out v (no or nc) r l r l r on + ----------------------- - = logic input v out r l com nc inh 300 35pf gnd v+ c no c l v+ add c isl43410
7 fn6044.4 may 12, 2008 logic input waveform is inverted for switches that have the opposite logic sense. figure 1c. address me asurement points repeat test for other switches. c l includes fixture and stray capacitance. figure 1d. address test circuit figure 1. switching times figure 2a. measurement poin ts figure 2b. test circuit figure 2. charge injection figure 3a. measurement points repeat test for other switches. c l includes fixture and stray capacitance. figure 3b. test circuit figure 3. break-before-make time test circuits and waveforms (continued) 50% t r < 20ns t f < 20ns t trans 90% 3v 0v 0v t trans logic input switch output 90% v out v out v (no or nc) r l r l r on + ----------------------- - = logic input v out r l com nc add 300 35pf gnd v+ c no c l v+ inh c v out v out off on off q = v out x c l switch output logic input 3v 0v c l v out r g v g gnd com no or nc v+ c logic input inh add 80% 3v 0v t d logic input switch output 0v v out t r < 20ns t f < 20ns logic input add com r l c l v out 35pf 300 no nc v+ gnd v+ c inh c isl43410
8 fn6044.4 may 12, 2008 detailed descriptions the isl43410 operates from a single 2v to 12v supply with low on-resistance (115 ) and high speed operation (t on = 60ns, t off = 30ns). the isl43410 is especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2.0v), low power consumption (3w), low leakage currents (5na max), and the tiny msop and qfn packaging. high frequency appl ications also benefit from the wide bandwidth, and the very high off-isolation (75db) and crosstalk rejection (-85db). supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and gnd (see figure 8). to prevent forward biasing these diodes, v+ must be applied before any input signals, and input signal voltages must remain between v+ and gnd. if these conditions cannot be guarant eed, then one of the following two protection methods should be employed. logic inputs can easily be protected by adding a 1k resistor in series with the input (see figure 8). the resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. this method is not applicable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see figure 8). these additional diodes limit the analog signal from 1v below v+ to 1v above gnd. the low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. figure 4. off-isolation test circuit figure 5. r on test circuit figure 6. crosstalk test circuit figure 7. capacitance test circuit test circuits and waveforms (continued) analyzer r l signal generator v+ c 0v or v+ no or nc com add gnd inh 0v or v+ v+ c 0v or v+ no or nc com add gnd v nx v 1 r on = v 1 /1ma 1ma inh 0v or v+ analyzer v+ c no1 or nc1 signal generator r l gnd add com1 50 nc com2 no2 or nc2 inh v+ c gnd no or nc com add impedance analyzer 0v or v+ inh isl43410
9 fn6044.4 may 12, 2008 . power-supply considerations the isl43410 construction is typical of most cmos analog switches, except that they have only two supply pins: v+ and gnd. v+ and gnd drive the in ternal cmos switches and set their analog voltage limits. unlike switches with a 13v maximum supply voltage, the isl43410?s 15v maximum supply voltage provides plenty of room for the 10% tolerance of 12v supplies, as well as room for overshoot and noise spikes. the minimum recommended supply voltage is 2.0v. it is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. refer to the electrical specification? tables beginning on page 3 and ?typical performance curves? on page 10 for details. v+ and gnd also power the internal logic and level shifters. the level shifters convert the in put logic levels to switched v+ and gnd signals to drive the analog switch gate terminals. this device cannot be operated with bipolar supplies because the input switching point becomes negative in this configuration. logic-level thresholds the isl43410 is ttl compatible (0.8v and 2.4v) over a supply range of 3v to 11v (see figure 11). at 12v, the v ih level is about 2.5v. this is still below the ttl guaranteed high output minimum level of 2.8v, but noise margin is reduced. for best results with a 12v supply, use a logic family that provides a v oh greater than 3v. the digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails (see figure 12). driving the digital input signals from gnd to v+ with a fast transition time minimizes power dissipation. the isl43410 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0v to v+). for example, driving the device with 3v logic (0v to 3v) while operating with a 5v supply, the device draws only 10a of current (see figure 12 for v in = 3v). similar devices of competitors can draw 8x this amount of current. high-frequency performance in 50 systems, signal response is reasonably flat even past 100mhz (see figure 17). figure 17 also illustrates that the frequency response is very cons istent over a wide v+ range, and for varying analog signal levels. an off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch?s input to its output. off-isolation is the resistance to this feed through, while crosstalk indicates the amount of feed through fr om one switch to another. figure 18 details the high off-isolation and crosstalk rejection provided by this fam ily. at 10mhz, off-isolation is about 55db in 50 systems, decreasing approximately 20db per decade as frequency increases. higher load impedances decrease off-isolation and crosstalk rejection due to the voltage divider action of the switch off impedance and the load impedance. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both v+ and gnd. one of these diodes conducts if any analog signal exceeds v+ or gnd. virtually all the analog leakage current comes from the esd diodes to v+ or gnd. although the esd diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or gnd and the analog signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and gnd pins constitutes the analog-signal-path leakage current. all analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given sw itch can show leakage currents of the same or opposite polarity. there is no connection between the analog signal paths and v+ or gnd. gnd v com v no or nc optional protection v+ in diode optional protection diode optional protection resistor for logic inputs 1k add 1k figure 8. overvoltage protection isl43410
10 fn6044.4 may 12, 2008 typical performance curves t a = +25c, unless otherwise specified. figure 9. on-resistance vs supply voltage figure 10. on-resistance vs switch voltage figure 11. digital switching point vs supply voltage figure 12. supply current vs digital address input voltage figure 13. turn-on time vs supply voltage figure 14. turn-off time vs supply voltage 25791112 0 100 200 300 400 500 r on ( ) v+ (v) v com = (v+) - 1v i com = 1ma -40c +85 c +25 c 3 4 6 8 10 13 r on ( ) v com (v) 0 4 6 8 10 12 2 v+ = 3.3v i com = 1ma 30 40 50 60 70 80 +85 c -40 c +25 c v+ = 12v 60 80 100 120 140 +25 c -40 c +85 c v+ = 5v 75 100 150 200 225 175 125 +25 c -40 c +85 c v+ (v) 25 3.0 2.5 2.0 1.5 1.0 0.5 3 4 6 7 8 9 10111213 v inh and v inl (v) 3.0 2.5 2.0 1.5 1.0 0.5 -40 c v inl 85 c -40 c +85 c v inh +25 c +25 c 01.5 0.5 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 140 120 100 80 60 40 20 0 v in(add) (v) i cc ( a) v+ = +5v v+ (v) 23456789101112 v com = (v+) - 1v t on (ns) 50 100 150 200 250 300 350 0 -40 c +85 c +25 c t off (ns) v+ (v) 23456789101112 v com = (v+) - 1v 10 20 30 40 50 60 70 80 90 100 110 120 +85 c -40 c +25 c isl43410
11 fn6044.4 may 12, 2008 die characteristics substrate potential (powered up): gnd transistor count: 193 process: si gate cmos figure 15. address trans time vs supply voltage figure 16. charge injection vs switch voltage figure 17. frequency response figure 18. crosstalk and off-isolation typical performance curves t a = +25c, unless otherwise specified. (continued) v+ (v) 23456789101112 v com = (v+) - 1v t trans (ns) 50 100 150 200 250 300 350 0 -40 c +85 c +25 c 024681012 -5 -4 -3 -2 -1 0 1 2 3 q (pc) v com (v) v+ = 3.3v v+ = 5v v+ = 12v frequency (hz) +3 0 -3 normalized gain (db) gain phase 0 45 90 135 180 phase () 1m 10m 100m 600m r l = 50 v in = 0.2v p-p (v+ = 13v) v in = 5v p-p (v+ = 13v) v in = 0.2v p-p (v+ = 3v) v in = 2.5v p-p (v+ = 3v) frequency (hz) 1k 100k 1m 100m 500m 10k 10m -110 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 crosstalk (db) off-isolation (db) 110 10 20 30 40 50 60 70 80 90 100 isolation crosstalk v+ = 3v to 12v isl43410
12 fn6044.4 may 12, 2008 isl43410 package outline drawing l16.3x3 16 lead quad flat no-lead plastic package rev 2, 4/07 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view bottom view side view ( 2. 80 typ ) ( 1. 50 ) (4x) 0.15 6 pin 1 index area 3.00 0 . 00 min. 0 . 05 max. ( 16x 0 . 60) ( 16x 0 . 23 ) c 0 . 2 ref 5 16x 0.40 0.10 0 . 90 0.1 ( 12x 0 . 5 ) 3.00 9 8 b a 12 1.5 12x 0.50 4x 13 seating plane 0.08 c see detail "x" base plane c 0.10 16x 0.23 0.10 5 4 4 - 0.05 + 0.07 b c ma 1 .50 0 . 15 c pin #1 index area 1 16 6
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6044.4 may 12, 2008 isl43410 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m10.118 (jedec mo-187ba) 10 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.020 bsc 0.50 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n10 107 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 5 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 0 12/02

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